The present invention relates to the manufacture and handling of relatively large sheets of material and/or structures, such as semiconductor-on-insulator (SOI) structures.
Semiconductor on insulator devices are becoming more desirable as market demands continue to increase. SOI technology is becoming increasingly important for high performance thin film transistors (TFTs), solar cells, and displays, such as, active matrix displays, organic light-emitting diode (OLED) displays, liquid crystal displays (LCDs), integrated circuits, photovoltaic devices, etc. SOI structures may include a thin layer of semiconductor material, such as silicon, on an insulating material.
Various ways of obtaining SOI structures include epitaxial growth of silicon (Si) on lattice matched substrates, and bonding a single crystal silicon wafer to another silicon wafer. Further methods include ion-implantation techniques in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer as in the case of hydrogen ion implantation.
U.S. Pat. No. 7,176,528 discloses a process that produces an SOG (semiconductor on glass) structure. The steps include: (i) exposing a silicon wafer surface to hydrogen ion implantation to create a bonding surface; (ii) bringing the bonding surface of the wafer into contact with a glass substrate; (iii) applying pressure, temperature and voltage to the wafer and the glass substrate to facilitate bonding therebetween; and (iv) separating the glass substrate and a thin layer of silicon from the silicon wafer.
The above manufacturing process as well as additional pre-bonding and post binding processes require that the semiconductor wafers, intermediate structures, the initial SOI structures, and the final application specific structures (such as displays, etc.) be moved among a number of fabrication stations and/or machines. In some instances, it is required or desirable to transport or otherwise physically move the structures at elevated temperatures. In the case of moving SOI structures, particularly at temperature, great care must be taken to ensure that the semiconductor material and the insulator substrate (e.g., glass or glass ceramic) is not damaged or contaminated, e.g., by warping, sagging, and/or glass breakage. The challenges associated with careful handling of the SOI structures is exacerbated as the size of the SOI structure increases, such as is experienced when large sheets of glass substrates are covered by multiple semiconductor layers in a tiling arrangement. (Large area SOI structures are described in detail in, for example, U.S. Application Publication No. 2007/0117354, the entire disclosure of which is incorporated herein in its entirety.)
As mechanical transport devices, such as rollers, suction cups, metal grippers, etc. are not suitable for transporting SOI structures due to the potential for contamination and the high temperatures involved, a class of pickup devices, known as Bernoulli wands, has been employed for transporting very hot semiconductor wafers. Bernoulli wands (e.g., formed of quartz) are useful for transporting semiconductors wafers between high temperature chambers. The advantage provided by the Bernoulli wand is that the hot semiconductor wafer generally does not contact the pickup wand, except perhaps at one or more small locators positioned outside the wafer edge on the underside of the wand, thereby minimizing contact damage to the wafer caused by the wand. Bernoulli wands for high temperature wafer handling are disclosed in U.S. Pat. No. 5,080,549; U.S. Pat. No. 6,242,718; and U.S. Application Publication No. 2008/0025835, the entire disclosures of which are hereby incorporated herein by reference.
When positioned above a semiconductor wafer, the Bernoulli wand uses jets of gas to create a gas flow pattern above the semiconductor wafer that causes the pressure immediately above the semiconductor wafer to be less than the pressure immediately below the semiconductor wafer. Consequently, the pressure imbalance causes the semiconductor wafer to experience an upward “lift” force. Moreover, as the semiconductor wafer is drawn upward toward the wand, the same jets that produce the lift force produce an increasingly larger repulsive force that prevents the semiconductor wafer from contacting the Bernoulli wand. As a result, it is possible to suspend the semiconductor wafer below the wand in a substantially non-contacting manner.
Although the use of the Bernoulli wand has been helpful in transporting relatively small sized semiconductor wafers (e.g., in the 200-300 mm diameter range), the conventional usages of same are not suited to handling and transport of larger area SOI structures. Indeed, as the area of the SOI structure increases the use of conventional Bernoulli wand technology may still result in excessive warping, sagging, and/or glass breakage. Even relatively small area SOI structures may experience unnecessarily high curling and/or warping due to significant temperature gradients that occur when hot SOI structures are subject to the gas flow patterns of the conventional Bernoulli wand. Thus, in some manufacturing processes, such as the aforementioned anodic bonding process to form an SOI structure, an operator must wait for an SOI structure to cool significantly before subjecting the structure to transport via Bernoulli wand.
Accordingly, there is a need in the art for new methods and apparatus for handling sheet material (such as SOI structures), particularly at elevated temperatures.